Results-driven chip design engineer with 8+ years across semiconductors, automotive, and research. Passionate about building future AI products — from Liberty characterization to silicon that powers the next generation of intelligence.
I'm Devesh Kadambari — a chip enthusiast at heart who genuinely believes that the future of humanity is written in transistors. By day I'm a Senior Standard Cell Design Engineer at Intel, pushing the boundaries of what's possible on 3A and 18A process nodes. By night I'm out under the stars, wondering about the physics of the universe at a completely different scale.
My journey into semiconductors started with a fascination for how invisible structures smaller than a virus can orchestrate the entire digital world. That curiosity has never left me. Whether I'm characterizing Liberty models at 3nm or reading about the James Webb Telescope's latest deep-field image, I'm always chasing the edge of what's known.
I grew up between India and the US, and that cross-cultural perspective shapes how I collaborate — I've worked with teams across Sweden, USA, and India and genuinely believe diversity of thought builds better silicon. I care deeply about mentoring the next generation of engineers and believe great engineering teams are built on trust as much as talent.
When I'm not in the lab or staring at SPICE waveforms, you'll find me on a trail somewhere in the Bay Area, planning my next adventure, or setting up a telescope in a dark field trying to spot something no one around me has ever noticed before.
Amateur stargazer fascinated by cosmology, deep-sky objects, and space missions. Following JWST discoveries and dreaming of seeing the Milky Way core from a dark sky site.
Bay Area trail explorer — from the redwoods of Muir Woods to the ridgelines of Mission Peak. Nature resets the mind that spends its days thinking in nanometers.
Traveler with ties to India and a love for discovering new cultures, cuisines, and landscapes. Every new place is a fresh perspective on the world.
Genuinely excited about AI silicon, next-gen process nodes, and the race to build faster, more efficient chips. The future is being etched in atoms — and I want to be part of writing it.
Browse my work below.
Led end-to-end Liberty model file development (NLDM/CCST/CCSN) for Intel's most advanced process nodes. Pulled project in by a full quarter ahead of schedule in collaboration with IP, Graphics, and SoC teams — earning a recognition award.
Productized internal automation tools for circuit topology description and library release flows. Infrastructure eliminated manual errors and cut cycle time for 3A/18A library drops to IP and SoC stakeholders across Intel.
Designed a 3-layer Deep Neural Network in C++ and CUDA for object detection and face recognition. Trained on the COCO dataset using an NVIDIA TITAN Xp, achieving 61% recognition accuracy.
Designed and simulated a Surface Acoustic Wave Resonator FEM model in HFSS, characterizing EM fields, port impedance, and S-parameters from 1 MHz to 3 GHz. Achieved 95% power transfer improvement through ST-CUT Quartz tensor modeling.
Designed an ALU and SRAM unit with a multi-divided word line and shared data line incorporating low-power techniques at 45nm. Optimized for leakage and dynamic power while maintaining performance targets.
Reduced supply voltage from 1.1V to 0.7V across pipelined and parallel datapath configurations, trading area for doubled performance. Analyzed clock distribution, setup, propagation, and hold times for multi-processor configurations.
GPU Architecture & CUDA Programming, Advanced VLSI, Mixed-Signal VLSI, Computer Architecture, Static Timing Analysis, Operating Systems, Microprocessors II, Understanding of LLMs.
Foundational coursework in digital circuits, microprocessors, embedded systems, and electronic design. Concurrent with early graduate research in RF/MEMS resonator design and simulation.
Open to Staff-level roles at AI chip companies, semiconductor firms, and EDA/IP organizations. Passionate about AI silicon and next-generation process nodes.